The present invention relates to an electronic circuit for connecting a processor to a high-capacity memory in which the processor comprises a data bus of given width, for example 8-bits, for transferring data from and to the memory, and an address bus having a given width, for example 16 bits, for addressing the memory. In that way the processor can address a given number of bytes at a time, for example 64K.
An electronic circuit is known, in which a first part of the memory in which the basic program is stored is permanently connected to the processor while other parts or segments of the memory containing auxiliary programs are alternatively connected to the processor. Normally both the first part and the other parts or segments of the memory each have a capacity of 32 Kbytes, that is to say equal to half the total capacity which can be addressed by the processor. By way of the input/output port, the processor is capable of selecting that one of the other parts of the memory to associate with the first part which, as stated, is permanently connected thereto.
This known circuit however suffers from the disadvantage that only a part of the memory can be from time to time changed and associated with the processor while a large part thereof remains fixed. In addition, with the subdivision of the address space into only two blocks, execution of the programs is very slow and at times, the capacity of each block being greater than the individual auxiliary program contained therein, it is not always that the whole part of the memory is used.